STT-MRAM has received wide attention with its promising properties as the next generation memory. Over the years, with entering into nanometer technology, as process-temperature-voltage (PTV) variations being intensified increasingly, the read reliability of STT-MRAM becomes a critical problem. Therefore, it is highly required to design a sensing circuit with good sensing margin (SM) and anti-interference. This paper presents a dynamic reference (DR) and variation-tolerant sensing circuit for deep nanometer STT-MRAM. The circuit is composed with a clamp voltage generator (CVG), a dynamic reference generator (DRG), and a fully differential charge transfer amplifier (FDCTA). It is demonstrated that the proposed sensing circuit is capable of immunizing the PTV variations by increasing the sensing margin (SM) while lowering the read disturbance (RD). The sensing margin of the proposed circuit can be as high as 312 mV on condition of VDD to be 1.2 V and TMR value to be 150%.

中文翻译：

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用于深纳米 STT-MRAM 的动态参考和抗变化传感电路


STT-MRAM 作为下一代存储器因其具有前景的特性而受到广泛关注。多年来，随着进入纳米技术，工艺温度电压（PTV）变化日益加剧，STT-MRAM的读取可靠性成为一个关键问题。因此，非常需要设计具有良好感测余量（SM）和抗干扰性的感测电路。本文提出了一种用于深纳米 STT-MRAM 的动态参考 (DR) 和容变传感电路。该电路由钳位电压发生器（CVG）、动态参考发生器（DRG）和全差分电荷转移放大器（FDCTA）组成。结果表明，所提出的感测电路能够通过增加感测裕度 (SM) 同时降低读取干扰 (RD) 来免疫 PTV 变化。在 VDD 为 1.2 V、TMR 值为 150% 的条件下，所提出电路的感测裕度可高达 312 mV。