This article starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic array accelerator for the most frequently used Machine Learning algorithms needed in bandwidth-bound applications and a flexible-structure reprogrammable accelerator for less frequently used Machine Learning algorithms needed in latency-critical applications.

中文翻译：

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终极超级芯片上的终极数据流

本文从假设不久的将来 100BTransistor SuperComputers-on-a-Chip 将包括 N 个大型多核处理器、1000N 个小型众核处理器、一个类似 TPU 的固定结构脉动阵列加速器用于最常用的机器学习带宽受限应用程序所需的算法，以及用于延迟关键应用程序所需的不太常用的机器学习算法的灵活结构的可重新编程加速器。