Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secret key. In response, many locking techniques have been developed to specifically resist this form of attack. In this paper, we demonstrate two SAT modeling techniques that can provide many orders of magnitude speed up in discovering the correct key. Specifically, we consider relaxed encodings and symmetry breaking. To demonstrate their impact, we model and attack a state-of-the-art logic locking technique, Full-Lock. We show that circuits previously unbreakable within 15 days of run time can be solved in seconds. Consequently, in assessing the strength of any given locking, it is imperative that these modeling techniques be considered. To remedy this vulnerability in the considered locking technique, we demonstrate an extended version, logic-enhanced Banyan locking, that is resistant to our proposed modeling techniques.

中文翻译：

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逻辑锁定的建模技术

逻辑锁定是一种防止知识产权 (IP) 盗版的方法。然而，在合理的攻击模型下，基于 SAT 的方法已被证明在获取密钥方面是强大的。作为回应，已经开发了许多锁定技术来专门抵抗这种形式的攻击。在本文中，我们展示了两种 SAT 建模技术，它们可以在发现正确密钥方面提供许多数量级的加速。具体来说，我们考虑宽松的编码和对称性破坏。为了证明它们的影响，我们对最先进的逻辑锁定技术 Full-Lock 进行建模和攻击。我们表明，以前在运行时间的 15 天内牢不可破的电路可以在几秒钟内解决。因此，在评估任何给定锁定的强度时，必须考虑这些建模技术。