This paper presents a second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing the error-feedback (EF) structure. With the finite impulse response (FIR) filter based on a single operational transconductance amplifier (OTA), it realizes noise transfer function (NTF) zeros optimization. The specifications of OTA are relaxed without high-gain and fast-settling. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-coded 4-bit MSBs are implemented with the data weighted averaging (DWA) technique. The overall architecture is simple and robust. It does not need additional complicated digital calibrations, and only requires minor modifications to the standard SAR ADC. Design and simulation in a 130 ​nm CMOS process, the prototype consumes 96 ​μW of power when operating at 1 ​MS/s sampling frequency. The proposed ADC achieves peak Schreier FoM of 165 ​dB with 76.95 ​dB signal to noise and distortion ratio (SNDR) and 97.34 ​dB spurious free dynamic range (SFDR) at an oversampling ratio (OSR) of 8.

本文提出了一种采用误差反馈（EF）结构的二阶噪声整形逐次逼近寄存器（NS-SAR）模数转换器（ADC）。利用基于单个运算跨导放大器（OTA）的有限脉冲响应（FIR）滤波器，可实现噪声传递函数（NTF）零位优化。OTA的规格宽松，无需高增益和快速建立。为了减轻由电容器不匹配引起的谐波失真，温度计编码的4位MSB通过数据加权平均（DWA）技术实现。总体架构简单而强大。它不需要其他复杂的数字校准，只需要对标准SAR ADC进行少量修改。在130纳米CMOS工艺中进行设计和仿真，当以1 MS / s的采样频率运行时，原型功耗为96μW。拟议的ADC在过采样比（OSR）为8的情况下实现76.95 dB的信噪比和失真比（SNDR）和97.34 dB的无杂散动态范围（SFDR）达到165dB的峰值Schreier FoM。