The biggest challenge in the verification industry is to create a sufficient number of valid test cases to acquire the desired coverage closure. The design complexity is relentlessly increasing with the number of gates, IPs, embedded processors, software content, and many more. It diverts the research once again to a point, where verification needs a productivity boost to cope with increasing design complexity. The extensive SoC design verification processes are using different execution platforms like simulation, emulation and FPGA prototyping. Each of these platforms requires different ways of specifying tests. The productivity and time demand a single test intent to reuse it across all verification execution platforms. Universal verification methodology (UVM) provides a verification efficiency jump from directed tests to constraint random tests. Synthesis allows the design productivity to jump from gate level to RTL level. Similarly, the SoC verification needs a higher-level of abstraction for automation enactment across all execution platforms. The proposed work derives a test intent on a UVM register abstraction testbench to generate automated test cases. It also assists in the improved functional coverage metric through bug resistant algorithm. The testbench also saves the manual effort of writing test cases. The work improves the simulation time, CPU time, and functional coverage closure in lesser number of transactions as compared to state of the art test benches.

中文翻译：

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带有用于优化验证的寄存器头数据库的自动防错误测试意图

验证行业最大的挑战是创建足够数量的有效测试用例来获得所需的覆盖率闭包。设计复杂性随着门、IP、嵌入式处理器、软件内容等的数量不断增加。它再次将研究转移到一个点，验证需要提高生产力以应对日益增加的设计复杂性。广泛的 SoC 设计验证过程使用不同的执行平台，如仿真、仿真和 FPGA 原型设计。这些平台中的每一个都需要不同的方式来指定测试。生产力和时间需要一个单一的测试意图，以便在所有验证执行平台上重用它。通用验证方法 (UVM) 提供了从定向测试到约束随机测试的验证效率提升。综合允许设计生产力从门级跳到 RTL 级。同样，SoC 验证需要更高级别的抽象，以便在所有执行平台上实现自动化。拟议的工作在 UVM 寄存器抽象测试平台上导出测试意图，以生成自动化测试用例。它还通过抗错误算法帮助改进功能覆盖度量。测试平台还节省了编写测试用例的手动工作。与最先进的测试平台相比，这项工作在更少的事务中改进了模拟时间、CPU 时间和功能覆盖关闭。拟议的工作在 UVM 寄存器抽象测试平台上导出测试意图，以生成自动化测试用例。它还通过抗错误算法帮助改进功能覆盖度量。测试平台还节省了编写测试用例的手动工作。与最先进的测试平台相比，这项工作在更少的事务中改进了模拟时间、CPU 时间和功能覆盖关闭。拟议的工作在 UVM 寄存器抽象测试平台上导出测试意图，以生成自动化测试用例。它还通过抗错误算法帮助改进功能覆盖度量。测试平台还节省了编写测试用例的手动工作。与最先进的测试平台相比，这项工作在更少的事务中改进了模拟时间、CPU 时间和功能覆盖关闭。