Interposer-based 2.5-dimensional integrated circuit (2.5D IC) is considered as a promising solution to problems like wire delay and power consumption faced by the semiconductor industry today. Since the interconnect wires in the silicon interposer may be defective during fabrication and assembly, they must be adequately tested to ensure product qualification. This paper presents an efficient interconnect test architecture to detect open, short and delay faults, which is compatible with the IEEE 1149.1 standard. It provides a new boundary scan structure with low test power consumption. To reduce the overall test cost, a data-package based test structure is proposed to match the test data transfer volume between TSVs and scan chains. Interconnects of multiple dies can be tested simultaneously under constrains of test power with minimum external test pins. The simulation results validate the effectiveness of the proposed test method. We also present synthesis results to evaluate the area overhead.

基于中介层的2.5维集成电路（2.5D IC）被认为是当今半导体行业面临的诸如线延迟和功耗等问题的有前途的解决方案。由于硅中介层中的互连线在制造和组装过程中可能有缺陷，因此必须进行充分的测试以确保产品合格。本文提出了一种有效的互连测试架构，以检测开路，短路和延迟故障，该架构与IEEE 1149.1标准兼容。它提供了一种具有低测试功耗的新型边界扫描结构。为了降低总体测试成本，提出了一种基于数据包的测试结构，以匹配TSV和扫描链之间的测试数据传输量。可以使用最少的外部测试引脚在测试功率的约束下同时测试多个管芯的互连。仿真结果验证了所提出测试方法的有效性。我们还提出了合成结果来评估面积开销。