In this paper, the concept of integration of a high voltage trench MOSFET (HVT MOSFET) and low voltage trench MOSFET (LVT MOSFET) is proposed. Insulator (Dielectric) isolation technique is used for the implementation of HVT and LVT MOSFETs on Silicon-on-Insulator (SOI) layer side by side. The HVT MOSFET consists of two gates which are placed in separate trenches in the drift region. The proposed structure minimizes ON-resistance (R_on) along with increased breakdown voltage (V_br) due to reduced electric field, creation of dual channels, and folding of drift region in vertical direction. In HVT MOSFET, the drain current (I_D) increases leading to enhanced trans conductance (g_m) by simultaneous conduction of channels which improves the cut-off frequency (f_t) and maximum oscillation frequency (f_max). On the other side, LVT MOSFET consists of a gate placed within a SiO₂ trench to create two channels on either side of gate. The parallel conduction of two channels provides enhancement in I_D, g_m, f_max and f_t. The performance analysis of HVT MOSFET and LVT MOSFET is carried out using 2D simulation in the device simulator (ATLAS).

中文翻译：

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用于模拟/射频电路的SOI MOSFET的设计

本文提出了集成高电压沟槽MOSFET（HVT MOSFET）和低电压沟槽MOSFET（LVT MOSFET）的概念。绝缘体（电介质）隔离技术用于在绝缘体上硅（SOI）层上并排实现HVT和LVT MOSFET。HVT MOSFET由两个栅极组成，这两个栅极放置在漂移区的单独沟槽中。所提出的结构可将导通电阻（R _on）降至最低_，同时由于减小的电场，创建双通道以及垂直方向上的漂移区折叠而增加击穿电压（V _br）。在HVT MOSFET中，漏极电流（I _D）增加，从而导致跨导（g _m）通过同时传导通道来改善截止频率（f _t）和最大振荡频率（f _max）。另一方面，LVT MOSFET由放置在SiO ₂沟槽内的栅极组成，以在栅极的任一侧形成两个沟道。两个通道的并联导通可增强I _D，g _m， f _max和f _t。HVT MOSFET和LVT MOSFET的性能分析是在器件仿真器（ATLAS）中使用2D仿真进行的。