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Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods
Applied Physics Express ( IF 2.3 ) Pub Date : 2020-09-21 , DOI: 10.35848/1882-0786/abb68f
Eunjung Ko 1, 2 , Seon Haeng Lee 1 , Md. Hasan Raza Ansari 3 , Seung Wook Ryu 1 , Seongjae Cho 3
Affiliation  

The effects of precleaning processes by O 3 and SC-1 in depositing high- κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O 3 cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.

中文翻译:

栅极氧化物界面处理方法对28 nm逻辑晶体管的电性能和可靠性的依赖性

在实验比较研究中,密切研究了O 3和SC-1的预清洗工艺对沉积高κ栅极电介质的影响。该研究是在产品的28 nm技术节点上的p型MOSFET上进行的。O 3清洗显示出在反转操作模式下增加有效氧化物厚度,减少栅极泄漏并抑制待机泄漏电流的显着效果。分析了使用这两种不同的预清洗方法制造的PMOSFET的电性能,并评估了器件的可靠性。负偏压温度不稳定性寿命根据清洁方法显示出4倍的差异。
更新日期:2020-09-22
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