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Linkage Control Policy on Area Pacesetter and Active Compensation for Chip Angle Correction
IEEE Transactions on Components, Packaging and Manufacturing Technology ( IF 2.3 ) Pub Date : 2020-08-05 , DOI: 10.1109/tcpmt.2020.3014364
Tao Wu , Changhong Li , Weilin Ye , Fupei Wu , Bin Li

In order to improve the optical and electrical consistency in lighting and display, light emitting diode (LED) dies should be sorted and aligned precisely one by one. As per given current production process practices, the sorting efficiency is required to be more than 36 thousand units per hour (KUPH), while the alignment deviation should not exceed 1 mil (25.4 μm) and all dies' angle deviations should fall within 5°. Among all the requirements, the chip angle correction is particularly difficult to achieve because a small die correction on wafer would cause a change in all dies' positions, leading to significant performance degradation. This results in an ambiguity, due to the difficulty in balancing efficiency and accuracy. In this article, the influence factors of the accuracy deviation caused by the angle correction are analyzed in detail, and the negative effect caused by tiny deformation of the elastic substrate is studied with comprehensive experiments. The parallel scheduling mechanism of the angle correction is analyzed, and the influences on sorting performance are evaluated with stochastic petri net (SPN) model, so that the suitable working area is disclosed. A local compensation strategy using the local deformation trend of the membrane is utilized to optimize the accuracy of precorrection. Further, the alignment area is actively compensated according to the alignment precision requirements, so that the performance and accuracy requirements are balanced. In the chip packaging field, microchip angle correction is often needed. This method is applicable to similar situation and chips are adhesive on membrane.

中文翻译:


区域标头联动控制策略及切角修正主动补偿



为了提高照明和显示中的光学和电学一致性,发光二极管(LED)芯片需要一颗颗精确地分类和对齐。根据当前生产工艺实践,分选效率要求超过36,000件/小时(KUPH),同时对准偏差不应超过1密耳(25.4微米),所有模具的角度偏差应在5°以内。在所有要求中,芯片角度校正尤其难以实现,因为晶圆上的微小芯片校正会导致所有芯片位置发生变化,从而导致性能显着下降。由于难以平衡效率和准确性,这导致了歧义。本文详细分析了角度修正引起的精度偏差的影响因素,并通过综合实验研究了弹性基体微小变形带来的负面影响。分析了角度校正的并行调度机制,并利用随机Petri网(SPN)模型评估了其对分拣性能的影响,从而揭示了合适的工作区域。利用膜局部变形趋势的局部补偿策略来优化预校正的精度。进一步地,根据对位精度要求,对对位面积进行主动补偿,使得性能和精度要求达到平衡。在芯片封装领域,经常需要进行微芯片角度校正。此方法适用于类似情况且芯片粘在膜上。
更新日期:2020-08-05
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