We propose a dynamic programming algorithm that constructs delay-optimized circuits for alternating And-Or paths with prescribed input arrival times. Our algorithm fulfills best-known approximation guarantees and empirically outperforms earlier methods by exploring a significantly larger portion of the solution space. Our algorithm is the core of a new timing optimization framework that replaces critical paths of arbitrary length by logically equivalent realizations with less delay. Our framework allows revising early decisions on the logical structure of the netlist in a late step of an industrial physical design flow. Experiments demonstrate the effectiveness of our tool on 7nm real-world instances.

中文翻译：

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And-Or路径重构的组合逻辑延迟优化

我们提出了一种动态规划算法，该算法为具有规定输入到达时间的交替与或路径构建延迟优化电路。我们的算法通过探索解决方案空间的更大部分，实现了最著名的近似保证，并且在经验上优于早期的方法。我们的算法是新的时序优化框架的核心，该框架通过具有较少延迟的逻辑等效实现来替换任意长度的关键路径。我们的框架允许在工业物理设计流程的后期修改关于网表逻辑结构的早期决策。实验证明了我们的工具在 7nm 真实世界实例上的有效性。