This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by 2.02× as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is 1.75× times higher than the considered D2p11T cell. The proposed 10T cell shows 1.83× and 1.22× narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by 2.75× as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are 4.21× and 2.79× lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45nm technology file has been utilized to carry out simulations.

中文翻译：

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低功耗半选免费10T静态随机存取存储器单元的设计

本文介绍了一种设计低功耗和半选自由 10T 静态随机存取存储器单元 (SRAM) 的电路级技术。所提出的单元与单端读操作和差分写操作一起工作。所提出的位单元没有半选问题并且支持位交织格式。与传统的 6T SRAM 单元相比，所展示的 10T 单元的读取功耗降低了 40.75%，这归因于读取操作期间活动因子的降低。核心锁存器中使用的环路切割晶体管将写入信噪比 (WSNM) 提高了 14.94%，而读取解耦结构将读取信噪比 (RSNM) 提高了 14.94%2.02×与传统的 6T SRAM 相比。在所提议的工作中，提出了重要设计参数的可变性分析，例如读取电流、待机 SNM 和预计 10T SRAM 单元的读取功率，并与所考虑的拓扑进行了比较。3000 个样本的单元保持静态噪声容限的平均值为1.75×比考虑的 D2p11T 细胞高 1 倍。提议的 10T 细胞显示1.83×和1.22×与传统的 6T SRAM 单元相比，读取访问时间和写入访问时间分别更窄。已经研究了所提出的 10T 单元的读取电流与位线泄漏电流的比率，并通过以下方式进行了改进2.75×与传统的 6T SRAM 单元相比。建议的 10T 单元的写入功率延迟乘积和读取功率延迟乘积为4.21×和2.79×低于传统的 6T SRAM 单元。在这项工作中，使用 Generic Process Design Kit (GPDK) 45 的 cadence virtuoso 工具nm 技术文件已被用于进行模拟。