Traditionally, the data rate of a digital signal processing system is bound by the processing speed. In this article, a formal approach for overcoming this limitation and allowing high-data-rate applications to run on relatively slow processors is presented. This approach allows the time sampling period to be much shorter than the time required to process an input sample; in effect, an ultrahigh-speed system is obtained where the sample rate exceeds the processing rate by a factor controlled by the system designer. The proposed approach is applied to the multirate decimation algorithm and its associated dependence graph. A directed acyclic graph (DAG) is then obtained from it using a scheduling policy. The DAG is then partitioned using an interlaced partitioning scheme. Multiphase/multirate clocking is used to synchronize the different components of the system. The number of partitions required depends on the I/O rate and processor speed. The proposed approach speeds up the system at the expense of extra latency and hardware resources.

中文翻译：

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超高速抽取器的实现

传统上，数字信号处理系统的数据速率受处理速度的限制。在本文中，提出了一种克服此限制并允许高数据速率应用程序在相对较慢的处理器上运行的正式方法。这种方法允许时间采样周期比处理输入样本所需的时间短得多；实际上，获得了一个超高速系统，其中采样率超过了处理率一个由系统设计者控制的因素。所提出的方法应用于多速率抽取算法及其相关联的依赖图。然后使用调度策略从中获得有向无环图 (DAG)。然后使用隔行分区方案对 DAG 进行分区。多相/多速率时钟用于同步系统的不同组件。所需的分区数取决于 I/O 速率和处理器速度。所提出的方法以额外的延迟和硬件资源为代价来加速系统。