In today’s ChipMultiprocessors (CMPs), multiple cores share the common Last Level Cache (LLC), divided into multiple banks. As the data requirement is increasing the demand for larger LLC sizes is also increasing. The traditional SRAM technology is not area efficient to design such larger LLCs as demanded by the modern CMPs. From the last few years, DRAM technologies have been used to propose LLC. DRAM technology has almost 8 times density over the SRAM and hence larger cache size can be designed. Though DRAM is already considered as an alternative to design low cost, area-efficient larger size LLC, it must be used efficiently to get the benefits. Due to its overheads like access latency and refresh operations efficient techniques must be used to get better performance from DRAM LLC. In the existing works, it has been observed that though the larger LLC is required for the current as well as future data-intensive applications, the entire LLC may not be required while executing other applications. In such situations, some banks can be almost idle during a particular period of execution. These idle banks can be powered-off and restart later whenever required. The mechanism is called Cache Resizing as it resizes the cache (LLC) according to the current requirements. Cache resizing techniques are already proposed for SRAM based LLCs but due to the larger size of DRAM LLC, the same mechanisms cannot be used for DRAM LLCs. In this paper, we have proposed an efficient cache resizing policy for large sized LLC, especially for DRAM-based LLCs. We call our proposed cache resizing technique as Efficient Cache Resizing (ECR) which is implemented on top of a 3D Tiled CMP. Experimental analysis shows that ECR can reduce up to 44% more energy consumption as compared to the existing technique.

在当今的ChipMultiprocessors（CMP）中，多个内核共享公共的末级缓存（LLC），分为多个存储体。随着数据需求的增加，对更大的LLC尺寸的需求也在增加。传统的SRAM技术无法有效地设计现代CMP所需的更大的LLC。从最近几年开始，DRAM技术就被用于提出LLC。DRAM技术的密度是SRAM的近8倍，因此可以设计更大的缓存大小。尽管DRAM已经被认为是设计低成本，面积有效的大尺寸LLC的替代方案，但必须有效地使用它才能获得好处。由于其访问延迟和刷新操作等开销，必须使用高效的技术来获得DRAM LLC的更好性能。在现有作品中 已经观察到，尽管当前以及将来的数据密集型应用程序都需要更大的LLC，但是在执行其他应用程序时可能不需要整个LLC。在这种情况下，某些存储区可能在特定执行期间几乎处于闲置状态。这些空闲存储区可以关闭电源，并在以后需要时重新启动。该机制称为“缓存调整大小”，因为它会根据当前要求调整缓存（LLC）的大小。已经针对基于SRAM的LLC提出了缓存大小调整技术，但是由于DRAM LLC的尺寸较大，因此无法将相同的机制用于DRAM LLC。在本文中，我们为大型LLC（尤其是基于DRAM的LLC）提出了一种有效的缓存大小调整策略。我们将我们提出的缓存大小调整技术称为高效缓存大小调整（ECR），该技术在3D Tiled CMP之上实现。实验分析表明，与现有技术相比，ECR最多可减少44％的能耗。