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A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
Integration ( IF 2.2 ) Pub Date : 2020-09-16 , DOI: 10.1016/j.vlsi.2020.09.002
Bibin Sam Paul S , Antony Xavier Glittas , Lakshminarayanan Gopalakrishnan

In this paper, a low-complex chip to extract the Mel Frequency Cepstral Coefficient for a speech recognition system is presented. The architecture can operate in a continuous-flow manner to process streaming or the stored speech signal at high speed. The frame-overlap Hamming window, DFT and Mel-filter bank computations are deeply integrated to share memory buffers and avoid bit-reversal circuit to reduce area and latency. Moreover, normalised energy consumption and area delay product are reduced by 32%, and speed is increased by 5.2 times compared to prior works. Further, the fixed-point word-length is optimised to minimise the area without affecting the accuracy.



中文翻译:

低延迟模块级深度集成MFCC特征提取架构,用于语音识别

本文提出了一种低复杂度的芯片,用于提取语音识别系统的梅尔频率倒谱系数。该体系结构可以以连续流的方式操作以高速处理流传输或存储的语音信号。帧重叠的汉明窗,DFT和梅尔滤波器组计算已深度集成,以共享存储缓冲区,并避免使用位反转电路以减少面积和延迟。此外,与以前的工作相比,标准化的能耗和面积延迟积减少了32%,速度提高了5.2倍。此外,优化了定点字长以在不影响准确性的情况下最小化面积。

更新日期:2020-09-22
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