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A switchable DC offset cancellation circuit for time-based degradation correction
Analog Integrated Circuits and Signal Processing ( IF 1.2 ) Pub Date : 2020-09-16 , DOI: 10.1007/s10470-020-01714-w
Didem Erol , Ali Doğuş Güngördü , Günhan Dündar , Mustafa Berke Yelten

This paper focuses on observing the aging impact of a DC offset cancellation circuit (DCOC) on the performance of an amplifier subject to time-based degradation, also known as aging. The circuit can be activated or deactivated to reduce the offset voltage that arises due to possible mismatches between the aging transistor in an amplifier. The proposed DCOC is designed along with a fully differential amplifier. It is fabricated in the low power TSMC 40 nm CMOS technology by using a single power supply of 1.1 V. Post-layout simulation results demonstrate that the offset suppression can be realized both in the Monte Carlo (MC) and corner analysis. In the measurement results of the fabricated chips, the DC offset, which is present before the deactivation of the DCOC, is suppressed by 19.25 dB.



中文翻译:

可切换的直流偏移消除电路,用于基于时间的劣化校正

本文着重于观察DC偏移消除电路(DCOC)对放大器性能的时效影响,该性能会受到基于时间的退化(也称为时效)的影响。电路可以被激活或去激活以减少由于放大器中老化晶体管之间可能的失配而引起的失调电压。提出的DCOC与全差分放大器一起设计。它通过使用1.1 V单电源在低功率TSMC 40 nm CMOS技术中制造。布局后的仿真结果表明,可以在蒙特卡洛(MC)和拐角分析中实现偏移抑制。在制造的芯片的测量结果中,DCOC停用之前存在的DC偏移被抑制了19.25 dB。

更新日期:2020-09-16
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