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DMR-based Technique for Fault Tolerant AES S-box Architecture
arXiv - CS - Hardware Architecture Pub Date : 2020-09-11 , DOI: arxiv-2009.05329 Mahdi Taheri, Saeideh Sheikhpour, Mohammad Saeed Ansari and Ali Mahani
arXiv - CS - Hardware Architecture Pub Date : 2020-09-11 , DOI: arxiv-2009.05329 Mahdi Taheri, Saeideh Sheikhpour, Mohammad Saeed Ansari and Ali Mahani
This paper presents a high-throughput fault-resilient hardware implementation
of AES S-box, called HFS-box. If a transient natural or even malicious fault in
each pipeline stage is detected, the corresponding error signal becomes high
and as a result, the control unit holds the output of our proposed DMR voter
till the fault effect disappears. The proposed low-cost HFS-box provides a high
capability of fault-tolerant against transient faults with any duration by
putting low area overhead, i.e. 137%, and low throughput degradation, i.e.
11.3%, on the original implementation.
中文翻译:
基于 DMR 的容错 AES S-box 架构技术
本文介绍了 AES S-box 的高吞吐量容错硬件实现,称为 HFS-box。如果在每个流水线阶段检测到瞬时自然甚至恶意故障,相应的错误信号就会变高,因此,控制单元会保持我们提出的 DMR 投票器的输出,直到故障影响消失。所提出的低成本 HFS 盒通过将低区域开销(即 137%)和低吞吐量降级(即 11.3%)放在原始实现上,提供了针对任何持续时间的瞬态故障的高容错能力。
更新日期:2020-09-14
中文翻译:
基于 DMR 的容错 AES S-box 架构技术
本文介绍了 AES S-box 的高吞吐量容错硬件实现,称为 HFS-box。如果在每个流水线阶段检测到瞬时自然甚至恶意故障,相应的错误信号就会变高,因此,控制单元会保持我们提出的 DMR 投票器的输出,直到故障影响消失。所提出的低成本 HFS 盒通过将低区域开销(即 137%)和低吞吐量降级(即 11.3%)放在原始实现上,提供了针对任何持续时间的瞬态故障的高容错能力。