The next-generation internet routers need ultra high speed such as 1 Tbps to process increased internet traffic. Efficient table lookup is key to realize high-speed packet processing and Packet Processing Cache (PPC) was proposed for this purpose. However, PPC has not been well optimized in the view of architecture and its ability to improve table lookup has therefore been underestimated so far. In this paper, we revisit PPC to reveal its real potential in table lookup. For this, we apply three architecture-level optimization techniques (hierarchization, pipelining and port addition), which are widely used to improve throughput of caches in microprocessors, and their combinations to PPC. Through the analysis of hundreds of billions of candidates of PPC configurations, we clarify the impact of these optimization techniques on the design space of internet routers with PPC. Our experimental results show that our best configuration can achieve 1045.7 Gbps packet processing with the power of 4273.3 mW and the area of 50.20 mm${}^2$, which is 3.35x improvement in Gbps per watt when compared to conventional PPC.

下一代互联网路由器需要超高速（例如1 Tbps）来处理增加的互联网流量。有效的表查找是实现高速数据包处理的关键，为此提出了数据包处理缓存（PPC）。但是，从体系结构的角度来看，PPC尚未得到很好的优化，因此，到目前为止，其改善表查找的能力被低估了。在本文中，我们将重新审视PPC，以揭示其在表查找中的真正潜力。为此，我们应用了三种体系结构级别的优化技术（分层，流水线和端口添加），这些技术被广泛用于提高微处理器中的高速缓存及其PPC组合的吞吐量。通过分析数千亿个PPC配置的候选者，我们阐明了这些优化技术对具有PPC的Internet路由器设计空间的影响。我们的实验结果表明，我们的最佳配置可以实现1045.7 Gbps的数据包处理，功率为4273.3 mW，面积为50.20 mm${}^2$，与传统PPC相比，每瓦Gbps的性能提高了3.35倍。