In this paper a ternary half adder is proposed and designed using carbon nano-tube field effect (CNFET) transistors. This novel design in ternary logic is based on multiplexers and level converters. The performance of the proposed design is examined against different supply voltages and a range of temperatures and fan-outs. Propagation delay time, power consumption, power-delay product (PDP) and transistor count are compared between the proposed ternary half adder and prior works. It is shown that the delay time in the proposed design can be improved by 75% with respect to other works while the PDP can be improved at least by 5%. Moreover, the transistor count in the novel design is less than other works at least by 10%. Therefore, it can be a promising candidate for the design of next generation of adder circuits in digital logic systems and ALU blocks.

中文翻译：

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碳纳米管场效应晶体管（CNFET）技术中基于三元多路复用器的半加法器设计

本文提出并使用碳纳米管场效应（CNFET）晶体管设计了三元半加法器。这种新颖的三进制逻辑设计基于多路复用器和电平转换器。针对不同的电源电压以及一定范围的温度和扇出，检查了所提出设计的性能。在提议的三进制半加法器和先前的工作之间，比较了传播延迟时间，功耗，功率延迟乘积（PDP）和晶体管数。结果表明，相对于其他工作，所提出的设计中的延迟时间可以提高75％，而PDP至少可以提高5％。此外，新颖设计中的晶体管数量至少比其他作品少10％。因此，