Reduce is a fundamental computing pattern, which is widely involved in scientific and engineering applications. For example, accumulation, the most common example of reduce pattern, is the core of applications such as dot product, matrix multiplication, and finite impulse response (FIR) filter. However, there is a trade-off between performance and area in the hardware implementation of the reduce pattern. To solve this problem, we propose an optimized reduction method that can handle multiple arbitrary-length sets. The performance of the proposed method is evaluated for both a single data set and numerous data sets. Moreover, to quickly differentiate the data of different sets in the reduction circuit, individual modules are designed to manage the data. We implement the design on FPGAs and present the experimental results. The proposed design with high performance and low resource consumption can achieve at least 1.59 times improvement on area-time product compared with the reported methods.

中文翻译：

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FPGA上的资源和性能优化缩减电路

Reduce 是一种基础计算模式，广泛涉及科学和工程应用。例如，累加是最常见的归约模式示例，它是点积、矩阵乘法和有限脉冲响应 (FIR) 滤波器等应用的核心。但是，在缩减模式的硬件实现中，性能和面积之间存在权衡。为了解决这个问题，我们提出了一种优化的减少方法，可以处理多个任意长度的集合。所提出方法的性能针对单个数据集和多个数据集进行了评估。此外，为了快速区分还原电路中不同组的数据，设计了单独的模块来管理数据。我们在 FPGA 上实现了设计并展示了实验结果。