Shift registers are the essential elements that are capable of storing and transmitting the data in sequential mode in digital circuits. It consists of D flip-flops, which are connected in a successive manner and share the common clock pulse applied to each Flip-flop. However, the clock distribution network consumes the major portion among the whole power consumption. In this paper a novel clock pulse generation scheme, called as Multiplexer based Clock Pulse Generator (MCPG) is proposed to minimize the power consumption and reduce the silicon area occupation of the shift register by reconstructing the clock distribution network using MCPG. It generates multiple non overlapped clock pulses with minimum power utilization, less area and also resolves the inequality between arrival of clock pulse and data to the consecutive Flip-flops at different time. The proposed clock distribution method reduce area and overall power consumption up to 22% and 31% respectively, compared with shift registers implemented using conventional clocking methods. The optimized MCPG with Conditional Pass Logic Dynamic D Flip-flop(CPLDDFF) is also implemented in 256-bit arrayed shift register via an 8- bit Serial In Serial Out(SISO) sub shift register, save power up to 12%. The proposed system is realized using SPICE with CMOS 0.13 μm technology.

移位寄存器是能够在数字电路中以顺序模式存储和传输数据的基本元件。它由D个触发器组成，它们以连续的方式连接并且共享施加到每个触发器的公共时钟脉冲。但是，时钟分配网络消耗了整个功耗中的大部分。在本文中，提出了一种新颖的时钟脉冲生成方案，称为基于多路复用器的时钟脉冲发生器（MCPG），以通过使用MCPG重构时钟分配网络来最小化功耗并减少移位寄存器的硅面积占用。它生成具有最小功率利用率的多个非重叠时钟脉冲，较小的面积，还解决了时钟脉冲与数据在不同时间到达连续触发器之间的不平等问题。与使用常规时钟方法实现的移位寄存器相比，所提出的时钟分配方法分别将面积和总功耗分别降低了22％和31％。带有条件通过逻辑动态D触发器（CPLDDFF）的优化MCPG还通过8位串行输入串行输出（SISO）子移位寄存器在256位阵列移位寄存器中实现，可节省多达12％的功率。所提出的系统是使用SPICE和CMOS 0.13μm技术实现的。带有条件通过逻辑动态D触发器（CPLDDFF）的优化MCPG还通过8位串行输入串行输出（SISO）子移位寄存器在256位阵列移位寄存器中实现，可节省多达12％的功率。所提出的系统是使用SPICE和CMOS 0.13μm技术实现的。带有条件通过逻辑动态D触发器（CPLDDFF）的优化MCPG还通过8位串行输入串行输出（SISO）子移位寄存器在256位阵列移位寄存器中实现，可节省多达12％的功率。所提出的系统是使用SPICE和CMOS 0.13μm技术实现的。