Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band shift, a new subthreshold current model caused by the interface-trapped-charge is developed for the nanosheet FET. With the subthreshold current I_sub, the noise margin (NM) of the subthreshold logic gate composed of nanosheet FET is thoroughly evaluated. It is found that the positive interface-trapped-charge can degrade the high noise margin (NM_H) due to its increased/decreased subthreshold current of N-FET/P-FET. On the contrary, the negative interface-trapped-charge can decrease/increase subthreshold current of N-FET/P-FET, which hence deteriorates the low noise margin (NM_L). Both degradation of the subthreshold current and NM (i.e., ΔI_sub and ΔNM) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of α. With the minimum scaling factor α_min that allows for the minimum noise margin degradation (ΔNM), the minimum channel length L_min for the nanosheet FET can be obtained as it is readily applied for the subthreshold logic gate.

基于准3D势方法，准3D缩放理论，漂移扩散模型和等效平带位移，为纳米片FET开发了由界面俘获电荷引起的新的亚阈值电流模型。利用亚阈值电流I _sub，对由纳米片FET组成的亚阈值逻辑门的噪声容限（NM）进行了全面评估。已经发现，由于其正向界面俘获电荷会增加/减小N-FET / P-FET的亚阈值电流，因此会降低高噪声容限（NM _H）。相反，负的界面俘获电荷可以减少/增加N-FET / P-FET的亚阈值电流，因此会降低低噪声容限（NM _L）。亚阈值电流和NM（即ΔI_子和ΔNM）引起的短沟道效应（SCE的）可以通过α的适当选择缩放因子良好控制。用最小的比例因子α_分钟，其允许最小噪声余量降解（ΔNM），最小沟道长度L_分钟，因为它可容易地适用于亚阈值逻辑门可以得到纳米片FET。