The lower mobility for p-type Ge based is always an issue due to slow traps generation at the interface of the metal oxide semiconductor (MOS) device which designates the defects in films generated during the deposition process. One of the effective ways to reduce this slow traps generation is to perform post deposition annealing (PDA) at a certain temperature. However, the selection of proper annealing temperature is the key to reduce defects without damaging the film quality. The effect of different PDA temperatures on the slow traps generation mechanism in the GeON passivated Ge MOS device was examined in this work. The XPS spectra show the stable formation of GeON over Ge, while HRTEM does not show any effect of PDA at the interface of GeON/Ge. The slow trap density (ΔN_st) in HfO₂/GeON/Ge interface annealed at different temperatures was evaluated from the hysteresis curve of C-V sweep as the function of the effective oxide field. The lowest ΔN_st (4.01 × 10¹² cm⁻²) was observed for the PDA temperature for 400 ℃. While, ΔN_st increased slightly after PDA at 450 ℃. The work suggests that PDA at lower temperatures is essential to realize the high quality interface with lower interface trap density, enhanced mobility and lower CET in Ge based MOS devices. Further, it also helps to reduce the slow traps generations at the interface.

由于在金属氧化物半导体（MOS）器件的界面处缓慢产生陷阱，这表明在沉积过程中产生的膜中存在缺陷，因此p型Ge基迁移率较低始终是一个问题。减少这种缓慢陷阱产生的有效方法之一是在一定温度下执行沉积后退火（PDA）。然而，选择合适的退火温度是减少缺陷而不损害膜质量的关键。在这项工作中，研究了不同的PDA温度对GeON钝化Ge MOS器件中慢陷阱产生机理的影响。XPS光谱显示在Ge上方稳定形成GeON，而HRTEM在GeON / Ge界面上未显示PDA的任何作用。慢陷阱密度（ΔN _ST）中的HfO ₂根据CV扫描的磁滞曲线评估了在不同温度下退火的/ GeON / Ge界面与有效氧化物场的关系。最低ΔN _ST（4.01×10 ¹² 厘米^-2）观察为PDA温度为400℃。虽然，ΔN _ST小幅PDA后，在450℃提高。这项工作表明，在基于Ge的MOS器件中，较低的PDA对实现具有较低的界面陷阱密度，增强的迁移率和降低CET的高质量界面至关重要。此外，它还有助于减少界面处陷阱的缓慢产生。