Bottom–up-fabricated crossbars promise superior circuit density and 3-D integrability compared with the traditional CMOS-based implementations. However, their inherent stochasticity presents difficulties in building complex circuits from components that demand precise patterning and high registration accuracies. With fewer terminals than active devices, passive components offer higher device densities and registration tolerances, making them amenable to bottom–up synthesized nanocrossbars. Motivated by this preference for passivity, we explore, in this article, neuromorphic classifiers based on passive neurons and passive synapses. We demonstrate via SPICE simulations how a shallow network of the diode–resistor-based passive rectifier neurons and resistive voltage summers, despite its inherent inability to buffer, amplify, and negate signals, can recognize MNIST digits with 95.4% accuracy. We introduce weight-to-conductance mappings that enable negative weights to be implemented in hardware without excessive memory overheads. The influences of soft and hard defects on the classification performance are evaluated, and the methods to boost fault-tolerance are proposed. The first-order evaluation of the area, speed, and power consumption of the passive multilayer perceptron classifiers is undertaken, and the results are compared with a benchmark study in neuromorphic hardware.

中文翻译：

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多层感知器分类器的全被动硬件实现

与传统的基于 CMOS 的实现相比，自下而上制造的横杆保证了卓越的电路密度和 3-D 可集成性。然而，它们固有的随机性给从需要精确图案化和高配准精度的组件构建复杂电路带来了困难。与有源器件相比，无源器件的端子数量更少，可提供更高的器件密度和配准容差，使其适合自下而上的合成纳米交叉棒。受这种对被动性的偏好的启发，我们在本文中探索了基于被动神经元和被动突触的神经形态分类器。我们通过 SPICE 模拟演示了基于二极管电阻器的无源整流器神经元和电阻电压加法器的浅层网络，尽管其固有的无法缓冲、放大和抵消信号，可以以 95.4% 的准确率识别 MNIST 数字。我们引入了权重到电导的映射，使负权重能够在硬件中实现，而不会产生过多的内存开销。评估了软硬缺陷对分类性能的影响，并提出了提高容错能力的方法。对被动多层感知器分类器的面积、速度和功耗进行一阶评估，并将结果与​​神经形态硬件中的基准研究进行比较。并提出了提高容错能力的方法。对被动多层感知器分类器的面积、速度和功耗进行一阶评估，并将结果与​​神经形态硬件中的基准研究进行比较。并提出了提高容错能力的方法。对被动多层感知器分类器的面积、速度和功耗进行一阶评估，并将结果与​​神经形态硬件中的基准研究进行比较。