This paper presents the noise optimization of a novel switched-capacitor (SC) based neural interface architecture, and its circuit demonstration in a 0.13 $\mu\text{m}$ CMOS process. To reduce thermal noise folding ratio, and suppress $kT/C$ noise, several noise optimization techniques are developed in the proposed architecture. First, one parasitic capacitance suppression scheme is developed to block noise charge transfer from parasitic capacitors to amplifier output. Second, one recording path-splitting scheme is proposed in the input sampling stage to selectively record local field potentials (LFPs), extracellular spikes, or both for reducing input noise floor, and total power consumption. Third, an auto-zero noise cancellation scheme is developed to suppress $kT/C$ noise in the neural amplifier stage. A prototype neural interface chip was fabricated, and also verified in both bench-top, and In-Vivo experiments. Bench-top testings show the input-referred noise of the designed chip is 4.8 $\mu\text{V}$ from 1 $\text{Hz}$ to 300 $\text{Hz}$ , and 2.3 $\mu\text{V}$ from 300 $\text{Hz}$ to 8 $kHz$ respectively, and In-Vivo experiments show the peak-to-peak amplitude of the total noise floor including neural activity, electrode interface noise, and the designed chip is only around 20 $\mu\text{V}$ . In comparison with conventional architectures through both circuit measurement and animal experiments, it is well demonstrated that the proposed noise optimization techniques can effectively reduce circuit noise floor, thus extending the application range of switched-capacitor circuits.

中文翻译：

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基于开关电容器的神经接口的噪声优化技术。

本文介绍了一种新型基于开关电容器 (SC) 的神经接口架构的噪声优化，及其电路演示在 0.13 $\mu\text{m}$CMOS工艺。降低热噪声折叠率，抑制$千吨/加元噪声，在所提出的架构中开发了几种噪声优化技术。首先，开发了一种寄生电容抑制方案来阻止噪声电荷从寄生电容器转移到放大器输出。其次，在输入采样阶段提出了一种记录路径分割方案，以选择性地记录局部场电位 (LFP)、细胞外尖峰或两者，以降低输入噪声基底和总功耗。第三，开发了一种自动归零噪声消除方案来抑制$千吨/加元神经放大器阶段的噪声。制造了原型神经接口芯片，并在台式和体内实验。台式测试显示设计芯片的输入参考噪声为 4.8$\mu\text{V}$ 从 1 $\text{赫兹}$ 到 300 $\text{赫兹}$ , 和 2.3 $\mu\text{V}$ 从 300 $\text{赫兹}$ 到 8 $千赫$ 分别，和 体内 实验表明，包括神经活动、电极界面噪声在内的总本底噪声的峰峰值幅度，设计的芯片仅为20左右 $\mu\text{V}$ . 通过电路测量和动物实验与传统架构相比，很好地证明了所提出的噪声优化技术可以有效地降低电路本底噪声，从而扩展了开关电容器电路的应用范围。