The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.,An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2.,Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.,The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

中文翻译：

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具有集成折叠共源共栅运算放大器的 1 mm2 CMOS 流水线式 ADC

本文的目的是通过将有限的输入范围用于移动通信应用的 8 位流水线模数转换器 (ADC) 的较低开环直流增益运算放大器 (op-amp) 来证明可接受的性能.,具有折叠级联配置的运算放大器旨在提供最大的开环直流增益，而无需任何增益提升技术。通过布局前、布局后仿真和 ADC 测量的结果观察和分析低开环直流增益的影响。使用的制造工艺技术是 Silterra 0.18-µm CMOS 工艺。ADC 的硅面积为 1.08 mm2。，测量结果显示差分非线性 (DNL) 误差、积分非线性 (INL) 误差、信噪比 (SNR) 和无杂散动态范围 (SFDR) ) 在 -0.2 到 +0.2 LSB、-0 之间。0.4 Vpp 输入范围为 55 LSB，分别为 22 和 27 dB，2 MHz 输入信号的速率为 64 MS/s。静态功耗为 40 mW，电源电压为 1.8 V。ADC 的实验结果表明，通过将输入范围限制在 ±0.2 V，该 ADC 能够提供良好的合理性能。运算放大器的开环直流增益对 ADC 性能起着至关重要的作用。低开环直流增益会导致残留放大器的级增益误差，从而导致输出代码的非线性。然而，降低输入范围会将线性度提高到 ±0.2 LSB。该 ADC 能够提供良好的合理性能。运算放大器的开环直流增益对 ADC 性能起着至关重要的作用。低开环直流增益会导致残留放大器的级增益误差，从而导致输出代码的非线性。然而，降低输入范围会将线性度提高到 ±0.2 LSB。该ADC能够提供良好的合理性能。运算放大器的开环直流增益对 ADC 性能起着至关重要的作用。低开环直流增益会导致残留放大器的级增益误差，从而导致输出代码的非线性。然而，降低输入范围会将线性度提高到 ±0.2 LSB。