Reliability is a crucial requirement in any modern microprocessor to assure correct execution over its lifetime. As mission critical components are becoming common in commodity systems; e.g., control of autonomous cars, the demand for reliable processing has even further heightened. Latest process technologies even worsened the situation; thus, microprocessors design has become highly susceptible to reliability concerns. This paper examines asymmetric aging phenomenon, which is a major reliability concern in advanced process nodes. In this phenomenon, logical elements and memory cells suffer from unequal timing degradation over time and consequently introduce reliability concerns. So far, most studies approached asymmetric aging from circuit or physical design viewpoint, but these solutions were quite limited and suboptimal. In this paper we introduce an asymmetric aging aware micro-architecture that aims at reducing its impact. The study is mainly focused on the following subsystems: execution units, register files and the memory hierarchy. Our experiments indicate that the proposed solutions incur minimal overhead while significantly mitigating the asymmetric aging stress.

中文翻译：

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现代微处理器的不对称老化效应

可靠性是任何现代微处理器的关键要求，以确保其在其生命周期内正确执行。随着关键任务组件在商品系统中变得越来越普遍；例如，对自动驾驶汽车的控制，对可靠处理的需求甚至进一步提高。最新的工艺技术甚至使情况恶化；因此，微处理器的设计变得非常容易受到可靠性问题的影响。本文研究了不对称老化现象，这是先进工艺节点的主要可靠性问题。在这种现象中，逻辑元件和存储单元会随着时间的推移遭受不均衡的时序退化，从而引入可靠性问题。到目前为止，大多数研究都是从电路或物理设计的角度来处理不对称老化，但这些解决方案非常有限且次优。在本文中，我们介绍了一种旨在减少其影响的非对称老化感知微架构。研究主要集中在以下子系统：执行单元、寄存器文件和存储器层次结构。我们的实验表明，所提出的解决方案产生的开销最小，同时显着减轻了不对称老化应力。