Only by formal verification approaches functional correctness can be ensured. While for many circuits fast verification is possible, in other cases the approaches fail. In general no efficient algorithms can be given, since the underlying verification problem is NP-complete. In this paper we prove that for different types of adder circuits polynomial verification can be ensured based on BDDs. While it is known that the output functions for addition are polynomially bounded, we show in the following that the entire construction process can be carried out in polynomial time. This is shown for the simple Carry Ripple Adder, but also for fast adders like the Conditional Sum Adder and the Carry Look Ahead Adder. Properties about the adder function are proven and the core principle of polynomial verification is described that can also be extended to other classes of functions and circuit realizations.

中文翻译：

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PolyAdd：加法器电路的多项式形式验证

只有通过形式验证方法才能确保功能正确性。虽然对于许多电路，快速验证是可能的，但在其他情况下，这些方法会失败。一般来说，无法给出有效的算法，因为底层验证问题是 NP 完全的。在本文中，我们证明了对于不同类型的加法器电路，多项式验证可以基于 BDD 来保证。虽然已知加法的输出函数是多项式有界的，但我们在下面表明整个构造过程可以在多项式时间内完成。这适用于简单的进位波纹加法器，但也适用于条件和加法器和进位超前加法器等快速加法器。