A background calibration technique is proposed to correct bit weights in pipelined-successive-approximation-register (SAR) analogue-to-digital converters (ADCs). By splitting the second stage, the input signal interference is mostly removed, thereby greatly enhancing the convergence speed of the algorithm. Besides, the dither signal assists to eliminate mismatch issues between the partially split ADCs, thus relaxing the analogue overheads. According to the simulation, after calibration, the spurious-free-dynamic-range and signal-to-noise-and-distortion-ratio are improved from 53.2 to 88.2 dB and 49.5 to 75.2 dB, respectively. The calibration algorithm converges with about only 600 K samples.

中文翻译：

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使用部分分裂结构的具有快速收敛速度的流水线SAR ADC中基于抖动的比特权重校准

提出了一种背景校准技术来校正流水线连续逼近寄存器 (SAR) 模数转换器 (ADC) 中的位权重。通过第二阶段的分裂，大部分输入信号干扰被去除，从而大大提高了算法的收敛速度。此外，抖动信号有助于消除部分分离的 ADC 之间的失配问题，从而减轻模拟开销。根据仿真，校准后，无杂散动态范围和信噪失真比分别从53.2提高到88.2 dB和49.5到75.2 dB。校准算法收敛于大约只有 600 K 个样本。