Field Programmable Gate Arrays (FPGAs) provide complex embedded blocks to ease the development of high-performance computing systems for diverse area applications, including among others space, avionics and health. Although the rich set of features is ever expanding, there is one significant shortcoming of the SRAM-based FPGAs which concerns system designers for applications demanding high reliability: their vulnerability to Single Event Upsets (SEUs) which can cause system malfunction. In this work, we propose a placement approach to improve system reliability by reducing the execution time of configuration memory scrubbing, which can be used in conjunction with other reliability mechanisms proposed in the literature. The proposed placement approach is based on i) an automated floorplanning process to shape and locate the design region(s) and ii) a modified version of the Simulated Annealing placement algorithm aiming to reduce the scrubbing time. First, we performed a set of experiments with three QUIP benchmarks to demonstrate the efficiency of the proposed approach at different device utilization levels. Moreover, we illustrated its effectiveness for three different fault tolerance schemes, where scrubbing plays a different role in each one: i) a TMR microcontroller combined with scrubbing, ii) a soft processor protected by a low-cost mitigation scheme including scrubbing and checkpointing, iii) a JPEG encoder protected by a prioritized scrubbing scheduling scheme based on module criticality levels. The experimental results showed that the proposed approach improves system reliability in all the above schemes by reducing critical timing parameters, such as mean-time-to-detect and mean-time-to-repair. This reduction leads to a modest or high reliability improvement depending on the role of scrubbing in the adopted fault tolerance (FT) scheme.

中文翻译：

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用于可靠 FPGA 系统的擦洗感知布局

现场可编程门阵列 (FPGA) 提供了复杂的嵌入式块，以简化高性能计算系统的开发，用于不同领域的应用，其中包括空间、航空电子设备和健康。尽管丰富的功能集在不断扩展，但基于 SRAM 的 FPGA 存在一个显着缺点，这让系统设计人员担心需要高可靠性的应用程序：它们容易受到单事件翻转 (SEU) 的影响，这会导致系统故障。 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 在这项工作中，我们提出了一种放置方法，通过减少配置内存清理的执行时间来提高系统可靠性，该方法可以与文献中提出的其他可靠性机制结合使用。建议的布局方法基于 i) 自动布局规划过程来塑造和定位设计区域和 ii) 旨在减少擦洗时间的模拟退火布局算法的修改版本。首先，我们使用三个 QUIP 基准进行了一组实验，以证明所提出的方法在不同设备利用率水平上的效率。此外，我们展示了它对三种不同容错方案的有效性，其中清理在每个方案中扮演不同的角色：i) 与清理相结合的 TMR 微控制器，ii) 受低成本缓解方案保护的软处理器，包括清理和检查点， iii) JPEG 编码器，受基于模块重要性级别的优先清理调度方案保护。实验结果表明，所提出的方法通过减少关键时序参数，如平均检测时间和平均修复时间，提高了上述所有方案的系统可靠性。根据在采用的容错 (FT) 方案中擦除的作用，这种减少会导致适度或高度的可靠性改进。