SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). This paper deduces the read butterfly curve transfer function as an example to show the effect of supply voltage deviation. In order to increase the quantity of SRAM DUTs (Device under Tests) and test accuracy, we propose a test method with VDD correction which eliminates the effect of supply voltage deviation. First, an addressable test structure is applied, where the transmission gates are used to force and sense the node voltages, and then correct the voltages. Second, a test algorithm with fast convergence combining the bisection method and PID (Proportion Integral Differential) algorithm is proposed to correct the voltages. SPICE simulations show that the proposed method reduces the error from approximately 10% (commonly used methods) to less than 2%. It is further implemented in a standard 55nm CMOS process, and the static characteristic curves of 1k-bits SRAM DUTs are measured within the accuracy range of 1 mV, which fit well with the simulation results, indicating the method can accurately measure 1k-bits DUTs.

中文翻译：

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一种用于SRAM位单元静态稳定性测试的VDD校正方法

SRAM 稳定性是纳米 CMOS 技术中的一个主要问题。作为SRAM静态稳定性最重要的指标，SRAM的静态特性是通过静态特性曲线（读蝶形曲线、待机蝶形曲线、读N曲线、写N曲线和WNM曲线）推导出来的。本文以读取蝶形曲线传递函数为例，说明电源电压偏差的影响。为了增加SRAM DUT（被测设备）的数量和测试精度，我们提出了一种带有VDD校正的测试方法，可以消除电源电压偏差的影响。首先，应用可寻址测试结构，其中传输门用于强制和感测节点电压，然后校正电压。第二，提出了一种结合二分法和PID（比例积分微分）算法的快速收敛测试算法来校正电压。SPICE 仿真表明，所提出的方法将误差从大约 10%（常用方法）降低到小于 2%。进一步采用标准55nm CMOS工艺实现，在1 mV精度范围内测得1k-bits SRAM DUT的静态特性曲线，与仿真结果吻合良好，表明该方法可以准确测量1k-bits DUTs .