The division datapath is undoubtedly the most complex operation in a wide range of digital signal processing applications, such as in adaptive filtering algorithms. This paper proposes an optimized and approximate integer divider hardware architecture, based on the Newton–Raphson algorithm combining both fixed-point dynamic range and truncation techniques, to speed up that operation. Adaptive filters have been much studied over time, as they comprise one of the most challenging fields in signal processing. This work presents dedicated hardware architectures based on normalized least mean square adaptive filtering algorithms for the power line harmonics interference cancelling. The hardware architectures are based on 2’s complement representation and were described in VHDL and synthesized into a 65 nm CMOS dedicated ASIC. Our results show that the increased approximation level of Newton–Raphson divider approximation presents up to 223 times less power dissipation than the baseline version without our optimization and approximations, providing up to 93 times of power dissipation savings in the complete interference canceller system.

中文翻译：

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应用于 NLMS 自适应滤波器以实现高质量干扰消除的节能近似牛顿-拉夫森整数除法器

除法数据通路无疑是各种数字信号处理应用中最复杂的操作，例如自适应滤波算法。本文提出了一种优化的近似整数除法器硬件架构，基于结合了定点动态范围和截断技术的 Newton-Raphson 算法，以加速该操作。随着时间的推移，人们对自适应滤波器进行了大量研究，因为它们是信号处理中最具挑战性的领域之一。这项工作提出了基于归一化最小均方自适应滤波算法的专用硬件架构，用于电力线谐波干扰消除。硬件体系结构基于 2 的补码表示，并在 VHDL 中进行描述并合成为 65 nm CMOS 专用 ASIC。