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Two Behavioural Error Detection Techniques for the Cascaded Integrator–Comb Interpolation Filter Implemented on FPGA
Circuits, Systems, and Signal Processing ( IF 1.8 ) Pub Date : 2020-04-20 , DOI: 10.1007/s00034-020-01418-6
Kyle W. Gear , Alfonso Sánchez-Macián , Francisco Garcia-Herrero , Juan Antonio Maestro

The cascaded integrator–comb (CIC) filter is a key building block for communication and sample rate conversion systems that require efficient implementation. One such example is in satellite applications. Space applications have the problem of being highly susceptible to cosmic radiation, which in turn has the possibility of corrupting data. It is therefore necessary to devise techniques that detect errors with as little resource usage as possible in order to meet the usually strict constraints in space applications. Presented in this paper are two techniques derived from studying the behaviour of the interpolation version of the filter. The first being a parallel prediction technique improves upon DMR in terms of resource usage and offers very close error protection coverage. The second offers a trade-off of resource utilisation against error detection.



中文翻译:

在FPGA上实现级联积分器-梳状插值滤波器的两种行为错误检测技术

级联积分梳状(CIC)滤波器是要求有效实施的通信和采样率转换系统的关键组成部分。卫星应用就是这样一个例子。太空应用存在高度易受宇宙辐射影响的问题,而宇宙辐射又可能破坏数据。因此,有必要设计出以尽可能少的资源使用来检测错误的技术,以便满足空间应用中通常严格的约束。本文介绍了两种技术,它们是通过研究滤波器的插值版本的行为而得出的。第一种是并行预测技术,在资源使用方面改进了DMR,并提供了非常接近的错误保护范围。

更新日期:2020-04-20
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