In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of $$568\,\upmu \hbox {m} \times 298\,\upmu \hbox {m}$$ and consumes a power as less as $$0.28\,\upmu \hbox {W}$$ . It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step.

中文翻译：

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采用无源参考电荷共享和电荷累积技术的基于开关电容器的 SAR ADC

在这项工作中，提出了一种使用无源参考电荷共享和电荷累积的基于开关电容器的逐次逼近寄存器 (SAR) 模数转换器 (ADC)。对于 N 位分辨率，该架构的全差分版本仅需要 6 个电容器，这比传统的二进制加权 SAR ADC 有了显着改进。所提出的 SAR ADC 首先在 MATLAB 中建模，并通过行为仿真验证了实际运算跨导放大器限制（例如增益的有限值、单位增益带宽和压摆率）对 ADC 特性的影响。为了验证提议的 ADC 性能，我们设计并布局了一个 11 位 2 kS/s SAR ADC，采用 UMC 180 nm 1P6M CMOS 技术，电源电压为 1.8 V。总设计面积为 $568\，\upmu \hbox {m} \times 298\,\upmu \hbox {m}$$ 并且消耗的功率低至 $$0.28\,\upmu \hbox {W}$$ 。发现该 ADC 的积分非线性和微分非线性分别在 + 0.35/- 0.84 最低有效位 (LSB) 和 + 0.1/- 0.6 LSB 的范围内。此外，动态性能测试表明，建议的 SAR ADC 提供 10.14 的有效位数和 0.12 pJ/conv-step 的 Walden 品质因数 (FoMW)。