This paper presents a fixed point design and implementation of a low-complexity high-throughput digital predistorter (DPD) on FPGA. Based on the memory polynomial model , a parallel structure is proposed for the implementation of the DPD and the effects of the fixed-point implementation on the performance are analyzed employing fidelity metrics such as modulation error ratio and adjacent channel power ratio . According to this analysis, an optimized fixed-point hardware implementation of the proposed DPD with proper word lengths is presented. Besides some simplifications to the proposed structure, a number of effective modifications are proposed for clock enhancement. The improved clock frequency of the proposed implementation makes it a fit choice for application over communication signals with considerable bandwidth. The required hardware and the maximum clock rate corresponding to these modifications are evaluated and reported. The performance of the proposed DPD in linearization of an actual power amplifier (PA) is also experimentally evaluated, through application of an appropriate hardware setup. Experimental results show about 11 dB ACPR improvement in the PA output for a 128-QAM test signal. The moderate hardware resource requirement of the proposed high-throughput DPD is also verified through comparison with some remarkable works in the same area.

中文翻译：

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用于功率放大器线性化的数字预失真器的高效 FPGA 实现

本文介绍了一种基于 FPGA 的低复杂度高吞吐量数字预失真器 (DPD) 的定点设计和实现。在记忆多项式模型的基础上，提出了DPD实现的并行结构，并利用调制误差率、邻道功率比等保真度指标分析了定点实现对性能的影响。根据这一分析，提出了具有适当字长的建议 DPD 的优化定点硬件实现。除了对所提出的结构进行一些简化外，还提出了许多有效的修改来增强时钟。所提出的实现的改进时钟频率使其成为具有相当大带宽的通信信号应用的合适选择。评估并报告与这些修改相对应的所需硬件和最大时钟速率。通过应用适当的硬件设置，还通过实验评估了所提出的 DPD 在实际功率放大器 (PA) 线性化中的性能。实验结果表明，对于 128-QAM 测试信号，PA 输出的 ACPR 提高了大约 11 dB。通过与同一领域的一些杰出作品进行比较，也验证了所提出的高吞吐量 DPD 的适度硬件资源需求。实验结果表明，对于 128-QAM 测试信号，PA 输出的 ACPR 提高了大约 11 dB。通过与同一领域的一些杰出作品进行比较，也验证了所提出的高吞吐量 DPD 的适度硬件资源需求。实验结果表明，对于 128-QAM 测试信号，PA 输出的 ACPR 提高了大约 11 dB。通过与同一领域的一些杰出作品进行比较，也验证了所提出的高吞吐量 DPD 的适度硬件资源需求。