ESP is an open-source research platform for heterogeneous SoC design. The platform combines a modular tile-based architecture with a variety of application-oriented flows for the design and optimization of accelerators. The ESP architecture is highly scalable and strikes a balance between regularity and specialization. The companion methodology raises the level of abstraction to system-level design and enables an automated flow from software and hardware development to full-system prototyping on FPGA. For application developers, ESP offers domain-specific automated solutions to synthesize new accelerators for their software and to map complex workloads onto the SoC architecture. For hardware engineers, ESP offers automated solutions to integrate their accelerator designs into the complete SoC. Conceived as a heterogeneous integration platform and tested through years of teaching at Columbia University, ESP supports the open-source hardware community by providing a flexible platform for agile SoC development.

中文翻译：

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使用开放式 ESP 进行敏捷 SoC 开发

ESP 是用于异构 SoC 设计的开源研究平台。该平台将模块化的基于 tile 的架构与各种面向应用程序的流程相结合，用于加速器的设计和优化。ESP 架构具有高度可扩展性，并在规律性和专业化之间取得了平衡。配套方法提高了系统级设计的抽象级别，并支持从软件和硬件开发到 FPGA 上的全系统原型设计的自动化流程。对于应用程序开发人员，ESP 提供特定领域的自动化解决方案，为他们的软件合成新的加速器，并将复杂的工作负载映射到 SoC 架构上。对于硬件工程师，ESP 提供了自动化解决方案，将他们的加速器设计集成到完整的 SoC 中。