An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (Gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF++. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF++. It is found through experimental results that an ASIF++ is 4–9% area-efficient and requires 36% lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2–5 circuits. It also achieves 34–53% area saving as compared to a traditional FPGA.

中文翻译：

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具有缩小面积和静态存储单元的应用特定可重构架构

专用不灵活 FPGA (ASIF) 是针对给定一组已知电路的定制设计，它是通过大量减少 FPGA 的布线资源而生成的。在 ASIF 中，不同的动态可重配置应用电路最初在 FPGA 架构上进行映射和测试。随后，减少 FPGA 架构以实现已知应用电路的高效架构。然而，ASIF 的大部分仍然被完全灵活的逻辑块所占据，包含与传统 FPGA 中相同数量的区域和 SRAM 存储单元。因此，这里有进一步优化 ASIF 逻辑块的潜力，代价是移除或降低其可重构性。这项工作通过 SRAM 表共享技术优化了 ASIF 的逻辑块，在不影响其可重构性的情况下。此外，通过应用布尔函数（门）插入技术，进一步优化了 ASIF 的路由通道。所应用的技术（SRAM 表共享和布尔函数插入）不仅减少了面积、延迟和功耗，而且还最大限度地减少了重新配置时间、比特流大小和存储电路比特流所需的外部存储器的大小。这个优化版的 ASIF 被称为 ASIF++. 此外，需要对已知电路进行部分动态重新配置的片上系统中的嵌入式 FPGA 可以自动简化为 ASIF++. 通过实验结果发现，一个 ASIF++是 4–9%面积有效且需要36%与先前提出的一组 2-5 个电路的 ASIF 相比，SRAM 单元的数量更少。它还达到 34–53%与传统 FPGA 相比，节省空间。