To advance the energy efficiency of general digital computing far beyond the thermodynamic limits that apply to conventional digital circuits will require utilizing the principles of reversible computing. It has been known since the early 1990s that reversible computing based on adiabatic switching is possible in CMOS, although almost all of the "adiabatic" CMOS logic families in the literature are not actually fully adiabatic, which limits their achievable energy savings. The first CMOS logic style that achieved truly, fully adiabatic operation if leakage was negligible (CRL) is not fully static, which leads to a number of practical engineering difficulties in the presence of certain nonidealities. Later, "static" adiabatic logic families were described, but they were not actually fully adiabatic, or fully static, and were much slower. In this paper, we describe a new logic family, Static 2-Level Adiabatic Logic (S2LAL), which is, to our knowledge, the first CMOS logic family that is both fully static, and truly, fully adiabatic (modulo leakage). In addition, S2LAL is, we think, the fastest possible such family (among fully pipelined sequential circuits), having a latency per logic stage of one "tick" (transition time), and a minimum clock period (initiation interval) of 8 ticks. S2LAL requires 8 phases of a trapezoidal power-clock waveform (plus constant power and ground references) to be supplied. We argue that, if implemented in a suitable fabrication process designed to aggressively minimize leakage, S2LAL should be capable of demonstrating a greater level of energy efficiency than any other semiconductor-based digital logic family known today.

中文翻译：

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使用快速、全静态、全绝热 CMOS 进行可逆计算

为了将通用数字计算的能效提高到远远超出适用于传统数字电路的热力学限制，需要利用可逆计算的原理。早在 1990 年代初期，就已经知道基于绝热开关的可逆计算在 CMOS 中是可能的，尽管文献中几乎所有的“绝热”CMOS 逻辑系列实际上都不是完全绝热的，这​​限制了它们可实现的节能。如果泄漏可忽略不计 (CRL)，第一个实现真正、完全绝热操作的 CMOS 逻辑样式不是完全静态的，这会在某些非理想情况下导致许多实际工程困难。后来，描述了“静态”绝热逻辑族，但它们实际上并不是完全绝热的，或完全静态的，而且速度要慢得多。在本文中，我们描述了一个新的逻辑系列，即静态 2 级绝热逻辑 (S2LAL)，据我们所知，这是第一个既完全静态又真正完全绝热（模泄漏）的 CMOS 逻辑系列。此外，我们认为 S2LAL 是此类系列中最快的（在完全流水线化的时序电路中），每个逻辑阶段的延迟为 1 个“滴答”（转换时间），最小时钟周期（启动间隔）为 8 个滴答. S2LAL 需要提供 8 相梯形电源时钟波形（加上恒定电源和接地参考）。我们认为，如果采用旨在最大限度地减少泄漏的合适制造工艺，