In this work, a rationalized algorithm for calculating the quotient of two quaternions is presented which reduces the number of underlying real multiplications. Hardware for fast multiplication is much more expensive than hardware for fast addition. Therefore, reducing the number of multiplications in VLSI processor design is usually a desirable task. The performing of a quaternion division using the naive method takes 16 multiplications, 15 additions, 4 squarings and 4 divisions of real numbers while the proposed algorithm can compute the same result in only 8 multiplications (or multipliers in hardware implementation case), 31 additions, 4 squaring and 4 division of real numbers.

中文翻译：

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四元数除法算法

在这项工作中，提出了一种用于计算两个四元数的商的合理化算法，该算法减少了基础实数乘法的次数。用于快速乘法的硬件比用于快速加法的硬件昂贵得多。因此，减少 VLSI 处理器设计中的乘法次数通常是一项理想的任务。使用 naive 方法执行四元数除法需要 16 次乘法、15 次加法、4 次平方和 4 次实数除法，而所提出的算法只需 8 次乘法（或硬件实现情况下的乘法器）、31 次加法即可计算相同的结果，实数的4平方和4除法。