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FPGAD efender
ACM Transactions on Reconfigurable Technology and Systems ( IF 3.1 ) Pub Date : 2020-09-01 , DOI: 10.1145/3402937
Tuan Minh La 1 , Kaspar Matas 1 , Nikola Grunchevski 1 , Khoa Dang Pham 1 , Dirk Koch 1
Affiliation  

Sharing configuration bitstreams rather than netlists is a very desirable feature to protect IP or to share IP without longer CAD tool processing times. Furthermore, an increasing number of systems could hugely benefit from serving multiple users on the same FPGA, for example, for resource pooling in cloud infrastructures. This article researches the threat that a malicious application can impose on an FPGA-based system in a multi-tenancy scenario from a hardware security point of view. In particular, this article evaluates the risk systematically for FPGA power-hammering through short-circuits and self-oscillating circuits, which potentially may cause harm to a system. This risk includes implementing, tuning, and evaluating all FPGA self-oscillators known from the literature but also developing a large number of new power-hammering designs that have not been considered before. Our experiments demonstrate that malicious circuits can be tuned to the point that just 3% of the logic available on an Ultra96 FPGA board can draw the power budget of the entire FPGA board. This fact suggests a waste power potential for datacenter FPGAs in the range of kilowatts. In addition to carefully analyzing FPGA hardware security threats, we present the FPGA virus scanner FPGAD efender , which can detect (possibly) any self-oscillating FPGA circuit, as well as detecting short-circuits, high fanout nets, and a tapping onto signals outside the scope of a module for protecting data center FPGAs, such as Xilinx UltraScale+ devices at the bitstream level.

中文翻译:

FPGAD防御者

共享配置比特流而不是网表是保护 IP 或共享 IP 而不需要更长的 CAD 工具处理时间的非常理想的功能。此外,越来越多的系统可以极大地受益于在同一 FPGA 上为多个用户提供服务,例如,用于云基础设施中的资源池。本文从硬件安全的角度研究了恶意应用程序在多租户场景中对基于 FPGA 的系统造成的威胁。特别是,本文系统地评估了通过短路和自激振荡电路对 FPGA 功率冲击的风险,这可能对系统造成损害。这种风险包括实施、调整、并评估文献中已知的所有 FPGA 自振荡器,还开发了大量以前未考虑过的新功率锤击设计。我们的实验表明,恶意电路可以调整到只有 Ultra96 FPGA 板上可用逻辑的 3% 可以消耗整个 FPGA 板的功率预算的程度。这一事实表明数据中心 FPGA 在千瓦范围内的潜在浪费功率。除了仔细分析FPGA硬件安全威胁,我们还展示了FPGA病毒扫描仪FPGAD 这一事实表明数据中心 FPGA 在千瓦范围内的潜在浪费功率。除了仔细分析FPGA硬件安全威胁,我们还展示了FPGA病毒扫描仪FPGAD 这一事实表明数据中心 FPGA 在千瓦范围内的潜在浪费功率。除了仔细分析FPGA硬件安全威胁,我们还展示了FPGA病毒扫描仪FPGAD防御者,它可以检测(可能)任何自振荡 FPGA 电路,以及检测短路、高扇出网络以及对模块范围之外的信号的窃听,以保护数据中心 FPGA,例如 Xilinx UltraScale+ 设备比特流级别。
更新日期:2020-09-01
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