This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current I_on, while the off current I_off remains around an order lower, than that of an analogous equally-sized MOSFET at the same technology node. Higher I_on: I_off ratio and steeper sub-threshold slope of the proposed GOTFETs make them ideal candidates for ultra-low voltage applications like Schmitt trigger circuits. Considering the superior performance of the proposed GOTFET devices, simply replacing the MOSFETs with the proposed GOTFETs in conventional Schmitt trigger circuit significantly reduces the delays and static power consumption of the circuit as expected. At 0.4 V power supply voltage, there is 91.7% improvement in Power Delay Product (PDP) for Complementary GOTFET (CGOT) based conventional Schmitt trigger as compared to CMOS conventional Schmitt trigger for the same hysteresis width of 120 mV. In order to further minimize the dynamic power, a novel CGOT regenerative-latch Schmitt trigger design has also been presented in this paper for the first time, which further reduces the total (static + dynamic) power consumption and delays of the conventional Schmitt trigger circuit. The overall PDP in the proposed CGOT regenerative-latch based Schmitt trigger has been demonstrated to be merely 1.9% of (98.1% lower than) the PDP in corresponding CMOS conventional design.

本文介绍了一种创新的栅极重叠隧道FET（GOTFET）器件，它是一种先进的TFET，其设计产生的导通电流I _on约为两倍，而截止电流I _off仍比类似大小的导通电流低一个数量级。 MOSFET位于同一技术节点。更高我_上：我_关闭所建议的GOTFET的高比率和更陡峭的亚阈值斜率使其成为施密特触发电路等超低压应用的理想选择。考虑到建议的GOTFET器件的优越性能，在常规的施密特触发器电路中简单地用建议的GOTFET代替MOSFET可以显着减少电路的延迟和静态功耗。在电源电压为0.4 V的情况下，与相同的120 mV磁滞宽度的CMOS传统施密特触发器相比，基于互补GOTFET（CGOT）的传统施密特触发器的功率延迟乘积（PDP）提高了91.7％。为了进一步减小动态功率，本文还首次提出了一种新颖的CGOT再生锁存施密特触发器设计，这进一步降低了常规施密特触发器电路的总（静态+动态）功耗和延迟。在基于CGOT再生锁存器的施密特触发器中，整个PDP已被证明仅为相应CMOS传统设计中PDP的1.9％（比其低98.1％）。