Hold timing closure is an important milestone at the physical design phase of every Application Specific Integrated Circuit (ASIC). Many approaches have been proposed by different researchers and commercial Electronic Design Automation (EDA) providers to fix hold timing violations, but there has been no effort to study the impact of each technique on power consumption. Nowadays, the rise of low power applications demand keeps pushing for the invention of new power reduction techniques. In this paper, we presented a novel approach for power consumption reduction by reducing the power increase seen during the hold timing optimization. A sample of 100 industrial post-CTS designs from different applications and fabrication process technologies (from 180 nm to 28 nm) was used to measure the ratios of Δpower/Δhold_timing and Δarea/Δhold_timing of each technique. The ratios were calculated after legalization and global routing to include not only the power/area added directly by the hold optimization, but also the power/area increases induced indirectly by the additional timing fixes needed after placement legalization and routing repair. By considering the impact on power consumption and area increase of each technique while optimizing the design we have reduced substantially the power increase and the area overhead caused by the hold fixing. Experimental results show a power reduction of 7%, and an area reduction of 1% on average, with a beneficial impact on hold timing and a neutral impact on setup timing.

保持时序收敛是每个专用集成电路（ASIC）物理设计阶段的重要里程碑。不同的研究人员和商业电子设计自动化（EDA）提供商已经提出了许多方法来解决违反保持时序的问题，但是一直没有努力研究每种技术对功耗的影响。如今，低功率应用需求的增长一直推动着新功率降低技术的发明。在本文中，我们提出了一种通过减少在保持时序优化过程中看到的功率增加来降低功耗的新颖方法。来自不同应用和制造工艺技术（从180 nm到28 nm）的100种工业CTS后设计的样本用于测量每种技术的Δpower/Δhold_timing和Δarea/Δhold_timing的比率。这些比率是在合法化和全局布线后计算的，不仅包括通过保持优化直接添加的功率/面积，而且还包括在布局合法化和布线修复后，由于需要额外的时间定位而间接导致的功率/面积增加。通过在优化设计的同时考虑对每种技术的功耗和面积增加的影响，我们大幅降低了由于固定而导致的功耗增加和面积开销。实验结果表明，功率降低了7％，面积平均降低了1％，