Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area–delay product and 28.7% in energy–delay product over the recent Wallace tree adder which is the best among available multi-operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.

中文翻译：

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区域延迟和节能多操作数二叉树加法器

在此，分析了基于纹波进位加法器（RCA）的二叉树加法器（BTA）的关键路径，以找到最小化延迟的可能性。根据分析结果，提出了针对BTA的新逻辑公式和RCA的相应设计。比较结果表明，所提出的RCA设计在面积，延迟和能量方面都比现有RCA具有更高的效率。利用这种RCA设计，提出了BTA结构。综合结果表明，与最近的华莱士树型加法器相比，拟议的32操作数BTA节省了22.5％的面积延迟积和28.7％的能源延迟积，这在可用的多操作数加法器中是最好的。作者还在最近的乘法器设计中应用了建议的BTA来评估其性能。综合结果表明，由于使用了建议的BTA，乘法器设计的性能得到了显着改善。因此，建议的BTA设计可能是开发用于信号和图像处理应用的面积，延迟和节能数字系统的更好选择。