This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device-level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous back-side-illuminated shared VTG pixel, which lacks the sidewall implantation for noise mitigation, photogenerated carriers were transferred to the floating diffusion (FD) region along with the interface. In the proposed pixel, the channel is separated from the interface, and photogenerated carriers are transferred with 10 nm distance from VTG. The proposed pixel has a complete charge transfer from the buried pinned photodiode to FD with 1274 e ⁻ /µm ² equilibrium full-well capacity. The conversion gain is 200 μV/e ⁻ and the signal-to-noise ratio is 37 dB.

中文翻译：

---

垂直传输门固定光电二极管像素中侧壁电荷分离的3D设备级仿真

这项研究提出了一种垂直侧壁注入技术，用于利用垂直传输门（VTG）降低CMOS图像传感器像素的噪声。像素性能通过3D设备级仿真进行评估。结论是，与以前类似的工作相比，拟议的像素输出对界面陷阱的敏感性较低。在先前的背照式共享VTG像素中，该像素缺少用于减轻噪声的侧壁注入，将光生载流子与界面一起转移到浮动扩散（FD）区域。在提出的像素中，通道与界面分离，并且光生载流子与VTG的距离为10 nm。所提出的像素具有从掩埋钉扎光电二极管与1274 E中的完整的电荷转移到FD ^- 个/μm ²平衡全井能力。转换增益是200μV/ E ^-和信噪比为37分贝。