The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8–12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

中文翻译：

---

基于交错流水线处理的灵活的硬件方法用于多核时间可预测的系统设计

该研究提出了一种基于硬件的方法来对时间可预测的电子嵌入式系统进行建模和设计。它解决了当代实时系统的多线程和多任务问题。作者提出了可重构系统体系结构的通用模板，该模板可以灵活地适应给定的应用程序。VERILOG已实现了系统架构的可综合和参数化模型。该体系结构基于类似于ARM的RISC解决方案，其核心（即核心）由具有交错机制的8-12级可重配置流水线构建。此核心是系统的基本构建块，可以复制。每个内核可以使用复制的寄存器文件处理多个硬件线程。整个结构具有期限控制机制，负责任务的执行 评价的可预测性。作者分析了所提出的存储系统的一致性和硬件线程之间的互操作性。已经开发了三种不同的静态调度算法，并在示例中进行了介绍。本研究包含仿真实验的结果以及Virtex-7 FPGA平台中硬件实现的摘要。作者研究了系统的时序参数，并指出了需要进一步研究的领域。