This study presents the analysis and design of reduced switching (RSw) activity mode successive approximation register (SAR) analogue-to-digital (A-to-D) algorithm. For given analogue-to-digital converter (ADC) specifications, RSw mode design is based on the observation that the signal variation in two successive samples becomes linear over a certain range of input frequencies. Hence, dispensable switching activity between the two samples can be eliminated by enabling periodic temporal reference to the converter. No prediction or logic circuitry is required to extract information from previous bits. However, there exists a trade-off between the input frequency and the sampling frequency. A design criterion is derived using numerical mathematics to skip evaluation of the optimum number of bits while maintaining the desired signal-to-noise and distortion ratio. The design criterion is validated through behavioural simulations using MATLAB/Simulink ^® . Furthermore, a fully differential 10-bit, 104 kS/s ADC is designed in a standard 180 nm CMOS technology to demonstrate circuit implementation of the RSw mode. In the RSw mode, power dissipation in the comparator and relevant digital circuitry decreases by 20%. The ADC achieves low-frequency effective number of bits of 9.7 bits and spurious free dynamic range of 68.3 dB. With 1.8 V supply voltage, average power dissipation in the core ADC is 2.54 μW; resulting in figure-of-merit of 29.3 fJ/conv-step.

中文翻译：

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降低SAR ADC的开关模式：具有周期性待机模式电路组件的SAR A-to-D算法的分析和设计

这项研究提出了减少开关（RSw）活动模式逐次逼近寄存器（SAR）模数（A-D）算法的分析和设计。对于给定的模数转换器（ADC）规格，RSW模式设计基于以下观察结果：两个连续样本中的信号变化在输入频率的特定范围内变为线性。因此，通过启用对转换器的周期性时间参考，可以消除两个样本之间的可有可无的切换活动。无需预测或逻辑电路即可从先前的位中提取信息。但是，在输入频率和采样频率之间需要权衡。使用数值数学可以得出设计标准，从而跳过对最佳位数的评估，同时保持所需的信噪比和失真比。通过使用MATLAB / Simulink的行为仿真来验证设计标准 ^® 。此外，采用标准的180 nm CMOS技术设计了全差分10位104 kS / s ADC，以演示RSw模式的电路实现。在RSw模式下，比较器和相关数字电路的功耗降低了20％。ADC的低频有效位数为9.7位，无杂散动态范围为68.3 dB。在电源电压为1.8 V的情况下，内核ADC的平均功耗为2.54μW。得出的品质因数为29.3 fJ / conv-step。