This article presents a piecewise linear approximation computation (PLAC) method for all nonlinear unary functions, which is an enhanced universal and error-flattened piecewise linear (PWL) approximation approach. Compared with the previous methods, PLAC features two main parts, an optimized segmenter to seek the minimum number of segments under the predefined software maximum absolute error (MAE), raising the segmentation performance to the highest theoretical level for logarithm, and a novel quantizer to completely simulate the hardware behavior and determine the required bit width and ${\text {MAE}}_{c}$ (MAE in circuits) for hardware implementation. In addition, the hardware architecture is also improved by simplifying the indexing logic, leading to nonredundant hardware overhead. The ASIC implementation results reveal that the proposed PLAC can improve all metrics without any compromise. Compared with the state-of-the-art methods, when computing logarithmic function, PLAC reduces 2.80% area, 3.77% power consumption, and 1.83% ${\text {MAE}}_{c}$ with the same delay; when approximating hyperbolic tangent function, PLAC reduces 6.25% area, 4.31% power consumption, and 18.86% ${\text {MAE}}_{c}$ with the same delay; when evaluating sigmoid function, PLAC reduces 16.50% area, 4.78% power consumption with the same delay, and ${\text {MAE}}_{c}$ ; and when calculating softsign function, PLAC reduces 17.28% area, 11.34% power consumption, 12.50% delay, and 33.28% ${\text {MAE}}_{c}$ .

中文翻译：

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PLAC：所有非线性一元函数的分段线性逼近计算

本文介绍了适用于所有非线性一元函数的分段线性逼近计算 (PLAC) 方法，这是一种增强的通用且误差平坦的分段线性 (PWL) 逼近方法。与之前的方法相比，PLAC 具有两个主要部分，一个优化的分割器，在预定义的软件最大绝对误差 (MAE) 下寻找最小的段数，将分割性能提高到对数的最高理论水平，以及一个新颖的量化器完全模拟硬件行为并确定所需的位宽和 ${\text {MAE}}_{c}$ （电路中的 MAE）用于硬件实现。此外，还通过简化索引逻辑来改进硬件架构，从而导致非冗余硬件开销。ASIC 实施结果表明，提议的 PLAC 可以在不妥协的情况下改进所有指标。与最先进的方法相比，在计算对数函数时，PLAC 减少了 2.80% 的面积、3.77% 的功耗和 1.83% ${\text {MAE}}_{c}$ 具有相同的延迟；逼近双曲正切函数时，PLAC 减少了 6.25% 的面积、4.31% 的功耗和 18.86% ${\text {MAE}}_{c}$ 具有相同的延迟；在评估 sigmoid 函数时，PLAC 在相同的延迟下减少了 16.50% 的面积，4.78% 的功耗，以及 ${\text {MAE}}_{c}$ ; 在计算softsign函数时，PLAC减少了17.28%的面积、11.34%的功耗、12.50%的延迟和33.28% ${\text {MAE}}_{c}$ .