Due to the increasing interconnect delay caused by shrinking wiring dimensions, modern synchronous many-core systems are now facing critical issues. Particularly, the power budget to propagate high-frequency clock signals across the chip is limited. It becomes more challenging using conventional metallic interconnects to deliver a clock with low uncertainties across active dies. This article proposes a novel hybrid wireless-wired clock distribution network, which improves the performance of ON-chip clock distribution significantly. By using embedded wireless clock transmitter and receiver designs, because of the high fan-out feature of the wireless clock transmission, the overall clock delay, skew, and power have been reduced. The proposed hybrid clock distribution scheme is verified through a novel test circuit by using Arm Mali-G77 GPU as an example. Experimental results indicate that the proposed clock distribution network exhibits a significant global delay reduction of up to 28.8%. Also, for the best case scenario, a maximum of 46.7% and 17.7% reduction in clock skew and power consumption, are identified, respectively. Thus, our proposed approach offers a promising solution to clock distribution for many-core integrated circuits, especially for high-performance systems.

中文翻译：

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一种用于多核系统的具有低功耗混合无线-有线时钟分配网络的有源硅中介层

由于布线尺寸缩小导致互连延迟增加，现代同步众核系统现在面临着关键问题。特别是，通过芯片传播高频时钟信号的功率预算是有限的。使用传统的金属互连在有源芯片上提供具有低不确定性的时钟变得更具挑战性。本文提出了一种新颖的混合无线有线时钟分配网络，显着提高了片上时钟分配的性能。通过使用嵌入式无线时钟发送器和接收器设计，由于无线时钟传输的高扇出特性，整体时钟延迟、偏差和功耗都得到了降低。以 Arm Mali-G77 GPU 为例，通过新颖的测试电路验证了所提出的混合时钟分配方案。实验结果表明，所提出的时钟分配网络表现出高达 28.8% 的显着全局延迟降低。此外，在最佳情况下，时钟偏差和功耗分别降低了 46.7% 和 17.7%。因此，我们提出的方法为众核集成电路的时钟分配提供了一种很有前景的解决方案，尤其是对于高性能系统。