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Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2020-09-01 , DOI: 10.1109/tvlsi.2020.3008424
Chua-Chin Wang , Kuan-Yu Chao , Sivaperumal Sampath , Ponnan Suresh

One of the most important functional units in digital circuitry for synchronization and measurement is time-to-digital converter (TDC) which always requires higher resolution and accuracy. In this brief, a process, voltage, temperature (PVT)-variation-insensitive TDC featured with a PVT detector is proposed. The PVT detector takes advantage of another delay line with optimized locking conditions to differentiate PVT corners. The proposed TDC is physically realized using a 90-nm CMOS process. On-silicon measurement results demonstrate 30-ps resolution, < 1.5 LSB INL/DNL, and 2.22 mW at 100 MHz and 1.2-V supply voltage.

中文翻译:

使用 90-nm CMOS 工艺的抗 PVT 变化低功耗时间数字转换器设计

用于同步和测量的数字电路中最重要的功能单元之一是时间数字转换器 (TDC),它总是需要更高的分辨率和精度。在这个简介中,提出了一种具有 PVT 检测器的过程、电压、温度 (PVT) 变化不敏感的 TDC。PVT 检测器利用具有优化锁定条件的另一条延迟线来区分 PVT 角。建议的 TDC 是使用 90 纳米 CMOS 工艺物理实现的。硅上测量结果表明,在 100 MHz 和 1.2 V 电源电压下,分辨率为 30 ps、< 1.5 LSB INL/DNL 和 2.22 mW。
更新日期:2020-09-01
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