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Area Efficient High Through-put Dual Heavy Metal Multi-Level Cell SOT-MRAM
IEEE Transactions on Nanotechnology ( IF 2.1 ) Pub Date : 2020-01-01 , DOI: 10.1109/tnano.2020.3012669
Karim Ali , Fei Li , S. Y. H. Lua , Chun-Huat Heng

This paper proposes a novel multi-level cell spin-orbit torque magnetic random-access memory (MLC SOT-MRAM) cell structure and validates its functionality and performance through simulation. The proposed memory cell comprises two uniform magnetic tunnel junctions (MTJs) that can be programmed separately by the energy efficient SOT technology through two different heavy metal electrodes. This permit employing both single and dual port architectures. The uniform cross-sectional area of the in-series MTJs stack simplifies the fabrication process. In addition, the cell structure requires only four terminals to successfully read and write the two bits. This allows accessing the two bits with only three access transistors, which achieves 25% smaller 1-bit effective area compared to the conventional single level cell (SLC) SOT-MRAM that requires four transistors. Simulation results based on an approximated dynamic model shows it offers nearly similar write energy consumption compared to the conventional SOT-MRAM.

中文翻译:

面积高效的高吞吐量双重金属多级单元 SOT-MRAM

本文提出了一种新颖的多级单元自旋轨道扭矩磁性随机存取存储器 (MLC SOT-MRAM) 单元结构,并通过仿真验证了其功能和性能。建议的存储单元包括两个均匀磁隧道结 (MTJ),可以通过节能 SOT 技术通过两个不同的重金属电极对它们进行单独编程。这允许采用单端口和双端口架构。串联 MTJ 堆栈的均匀横截面积简化了制造过程。此外,单元结构只需要四个终端就可以成功读写两位。这允许仅用三个访问晶体管访问两个位,与需要四个晶体管的传统单级单元 (SLC) SOT-MRAM 相比,其 1 位有效面积缩小了 25%。基于近似动态模型的仿真结果表明,与传统 SOT-MRAM 相比,它提供了几乎相似的写入能耗。
更新日期:2020-01-01
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