This brief presents a compact low-power programmable multi-pattern pseudo-random binary sequence (PRBS) generator. It is capable of producing 2⁷ – 1, 2¹⁵ – 1, 2²³ – 1 and 2³¹ – 1 test patterns to meet multiple testing requirements. To reduce power and area, the full-rate architecture with the truly-single-phase clock logic (TSPC) D-flip-flops (DFF) instead of the current-mode logic (CML) DFF is adopted. The multiplexer (MUX) merged TSPC DFF is proposed to avoid the delay of the MUX in conventional multiple pattern PRBS generators. Hence, the critical path delay is reduced, and thus, the maximum data rate can be improved. Fabricated in a 40-nm CMOS process (260-GHz ${f}_{T}$ ), this PRBS occupies a core active area of 0.0037 mm² and operates at a maximum data rate of 15 Gb/s. The measured power consumption is 8.778 mW with 1.1-V supply. The figure-of-merit (FoM) is 0.019 pJ/bit at the pattern length of 2³¹ – 1.

中文翻译：

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15-Gb/s 0.0037-mm2 0.019-pJ/位全速率可编程多模式伪随机二进制序列发生器

本简介介绍了一种紧凑型低功耗可编程多模式伪随机二进制序列 (PRBS) 发生器。它能够产生2 ⁷ – 1、2 ¹⁵ – 1、2 ²³ – 1和2 ³¹ – 1测试图案，以满足多种测试需求。为了降低功耗和面积，采用具有真正单相时钟逻辑 (TSPC) D 触发器 (DFF) 而非电流模式逻辑 (CML) DFF 的全速率架构。提出了多路复用器 (MUX) 合并 TSPC DFF 来避免传统多模式 PRBS 发生器中多路复用器的延迟。因此，减少了关键路径延迟，从而可以提高最大数据速率。采用 40-nm CMOS 工艺制造 (260-GHz ${f}_{T}$ )，此 PRBS 占用的核心有效面积为 0.0037 mm ²，并以 15 Gb/s 的最大数据速率运行。在 1.1V 电源下测得的功耗为 8.778 mW。在码型长度为 2 ³¹ – 1 时，品质因数 (FoM) 为 0.019 pJ/bit 。